1. Technical Field
The present invention relates to a control device for a Universal Serial Bus (USB) interface and to a control method thereof.
2. Description of the Related Art
USB interfaces allowing the transmission and reception of digital data are known in the state of the art; a typical USB interface is shown in FIG. 1. The interface includes two terminals, VM and VP, for inputting the data to be sent, the D+ and D− terminals for the data transmission and a terminal for inputting the OE signal to enable the data transmission; the USB interface includes a level shifter circuit 10 for shifting the level of the OE signal and of the data received on the VM and VP terminals, and driver circuitry 1 with drivers for the transmission of the data and drivers for the reception of the data. The driver which is typically used for the transmission of the data is the differential driver Dr which is controlled by the input OE signal. The driver circuit also includes a bias circuit 40 for biasing the differential driver Dr.
The differential driver Dr is normally switched off during the reception of the data in order to reduce the energy consumption of the USB interface. When the device must operate in a transmission mode, the OE signal is set at a low logic level and the bias circuit of the Dr driver is activated. However, the activation of said bias circuit requires a certain time period and the data transmission may not start before the differential driver Dr is biased, therefore the transmission starts with a certain delay.
In some applications the delay between the enabling of the driver and the start of the data transmission may not allow an appropriate bias of the differential driver Dr. In this case, the bias transistors of the Dr driver imply an anomaly in the transmission of the first bit of the packet of digital data to be transmitted, thus reducing the quality of the transmitted signal.
FIG. 2 shows a data packet PD transmitted through a USB interface on the D+ and D− terminals with the above disclosed anomaly; the signal 11 indicates the voltage signal on the line D+ while the signal 12 indicates the voltage signal on the line D−. The signals 11 and 12 are alternately at a high logic level (voltage of 3 Volts) and at a low logic level (voltage of 0 Volts); the transitions between the high and low state of the signals 11 and 12 are indicated by the corresponding letters K and J and the data packet PD ends with an end-of-packet signal EOP. In FIG. 2 the first bit of the data packet, which corresponds to a C transition, is transmitted over a longer time period D1 than the waiting time period Dm (i.e. the transmission time period of every other bit of the packet) because of the bias transistors of the Dr driver. The transmission time period D1 of the first bit of the packet PD has a great influence on the evaluation of the average ratio of data which is the basis for the construction of the eye diagram; the eye diagram is in fact used to verify whether the transmission of the packet complies with the desired specifications. The packet PD is segmented by using the average time of bits (inverse of the average ratio of data), i.e. the average time for the transmission of the bits in the packet, as a reference and it is overlapped after each segment to create the eye. The eye diagram in FIG. 3 is that obtained for the packet PD; an error in the evaluation of the bit time, due to the time D1 of the first bit, leads to the misalignment of the bits of the eye and to a wrong evaluation of the disturbances.